The fabrication of silicon based solar cells requires a number of specialized processes to occur in a specific order. Generally these processes include single crystalline silicon ingots grown in crystal growing furnaces or cast into multi-crystalline blocks in “directional solidification” furnaces. The result of these processes are long, 6-12″ diameter (or more) “sausage-shaped” single crystal masses called ingots, or multi-crystalline blocks, from which thin slices of silicon are cut transversely or diagonally with “wire saws” to form rough solar cell wafers. These wafers, whether made up of a single crystal or multiple crystals conjoined together, are then processed to form smooth, thin wafers of thickness in the 140 to 200 micro-meter range. Because of the scarcity of suitable silicon, the current trend is towards making the wafers thinner, currently 180-200 micrometers thick, with 120-140 on the horizon.
Finished raw wafers are then processed into functioning solar cells, capable of generating electricity by the photovoltaic effect. Wafer processing starts with various cleaning and etching operations, followed by a multi-stage process of diffusion which creates a semi-conducting “p-n”, junction diode, followed by a third process in which Aluminum paste coatings are screen printed on the wafer front and back sides and then fired into the p-n junction layer, where they act as collectors and grounds, respectively.
The diffusion process starts with doping the silicon substrate wafer, comprising a first stage of applying (coating) one or more types of dopant materials, e.g., a P or/and B-containing composition or compound, to the front and/or back side of the wafers, followed by a second stage of drying the dopant. In a third stage, the dry, dopant-coated wafers are then fired in a diffusion furnace to cause diffusion of the P atoms of the dopant composition into the Si (or other advanced material) wafer substrate to form a thin p-n junction layer.
In a fourth stage, the edges of the diffusion-fired wafers are then cleaned with a laser edge ablater, and the wafers are then coated on the front side with the so-called anti-reflective coating layer, currently blue or brown, depending on the coating materials. Finally, in a fifth stage, the wafers are then screen printed, front and back, with a silver and aluminum composition paste, respectively, which are then dried and fired in a firing furnace to form the fine grid of collectors and back surface contact layers, respectively.
This invention relates to the first and second stages of coating one or more types of dopant compositions to one or more surfaces of the wafers in preparation for being diffusion or co-diffusion fired. Currently, there are three principal modes of applying a phosphoric dopant: A) batch-type tube furnace operation in two stages, first oxidizing the wafer with oxygen at about 400° C., purging with N2 followed by injection of POCl3 gas at 850-1000° C., the total process time being extensive, taking about 30 minutes. In the POCl3 process the wafers are closely stacked back to back in pairs, on edge and oriented generally vertically in boats that are then pushed into the tube furnace in which they are exposed to POCl3 gas. The POCl3 gas process also results in a serious “edge effect,” in which the bottom and top edges have a heavier dopant deposition as compared to the center section. Both the top and bottom deposition areas are arc-shaped side-to-side each opposed corner being covered with a thinner web at top and bottom center joining the larger corner areas. This pattern is thought to be an artifact of the close spacing of the pair of wafers, being separated in the boats, by on the order of 3-6 mm.
The result for POCl3 gas batch processing is that the upper “A band”, center “B zone” and bottom “C band” each have relatively consistent resistance values when measured laterally across the wafer, but the values vary widely top zone to center to bottom zone, when measured vertically from top to bottom. In order to obtain better consistency across the wafer in both lateral and vertical directions and wafer to wafer, resistance values are sacrificed. That is, while high spot resistance values of 80 or higher can be achieved, the consistency is so very poor across the wafer and from wafer to wafer that the wafers can't be used. Thus, in production, the resistance values are backed off, typically down into the 40-55 range, and occasionally as high as 55-65 range.
There are also two aqueous solution processes, using very low concentrations, about 5%, H3PO4 (orthophosphoric acid) in water; B) spraying the acid solution onto the wafers via an ultrasonic nozzle; or C) passing the wafers through a “waterfall” of the acid solution. In these currently available systems, the wafers are dried in the doper unit.
In the spray or the waterfall aqueous low concentration acid process, the water is on the order of 95% of the solution used, the H3PO4 being the remaining 5%. At least one spray system employs a mixture of 5% acid, a small percentage of an alcohol as a surfactant, and the balance water. In this variant process, there is poor consistency, wafer-to-wafer, of the dopant coating, and likewise the post-fired diffusion layer is neither even nor consistent.
In both spray and waterfall systems, since so much water is used, there is an extensive drying period on the order of 3-5 minutes per wafer. In the waterfall system, and more recently in a “cloud” system announced by TechnoFimes of Italy, wafers are conveyed through the wetting and drying zones on a disposable roll of special paper. This special paper is required to keep the back side clean, but is single-use, being collected and disposed after the wafers are transferred to the diffusion furnace conveyor. In the ultrasonic spray system, there are two alternative conveyor modes: 1) an O-ring type belt system; and 2) a metal mesh belt system. In the latter, the acidic dopant composition spray comes in contact with the metal mesh and causes contamination of the back surface of the wafer. That necessitates an extra step of etching or ablation of the back surface after diffusion firing.
In addition to the spray and waterfall process problems and limitations, the relatively thick meniscus of fluid on the wafer surface can result in phosphate concentration variations across the wafer during the extended drying period, with the result that the dopant is not evenly coated on the wafer surface, thinner in the center and heavier at the edges. This drying process stage is both slow and difficult to control. In turn, concentration/thickness variations cause uneven thickness of the p-n junction layer formed during diffusion firing. During subsequent metallization firing of the collector grid paste, the fine collector grid lines must burn through the anti-reflective coating into the p-n junction layer. If the junction layer is irregular in thickness and there is burn-through of the collectors, the cell will be short-circuited.
While dopant applicators can be enlarged to increase throughput, the current mismatch in the field is on the order of 3×. That is, a standard doper unit producing 400 wafers per hour feeds a diffusion firing furnace having a 1200 wafer per hour capacity. Thus, the capital requirements at the doper stage must be tripled to keep pace. And, as firing furnace throughput increases, the doper application stage becomes an increasing production bottleneck and adverse capital drain.
Accordingly, there is an unmet need in the solar cell wafer processing art to improve the dopant application stage, both as to speed of application and uniformity, without employing single-use consumable paper transport substrates, without introducing other problems downstream in the overall solar cell wafer production process, and to accomplish this economically off a continuous process having a small equipment footprint, and to match dopant applicator system throughput to the increasing throughput demands of diffusion furnaces, keeping to a 1-to-1 or lower capital equipment ratio so that the doping process is not a solar cell production bottleneck, while producing doped wafers having consistently high resistance value both across each wafer and wafer to wafer.